In recent years, along with increased integration and increased functionality of semiconductor integrated circuits, enhancement in performance of analog-digital mixed-signal integration circuits on which analog signal processing circuits (analog circuits) and digital signal processing circuits (digital circuits) are integrated has become extremely important.
In a usual design method for the digital circuits, Complementary Metal Oxide Semiconductors (CMOS) including MOS transistors are used aiming for larger scale and lower power consumption. Accordingly, use of the MOS transistors is increasing for the analog circuits, too.
However, a MOS transistor has a drawback in that gm (mutual conductance) is low compared to a bipolar transistor. Therefore, compared to an analog circuit using the bipolar transistor, an analog circuit using the MOS transistor has a reduced gain (amplification rate of a signal) in the analog circuit, and current in the circuit increases when the same amount of gain as that in the case of using the bipolar transistor is obtained.
Moreover, in the case where the MOS transistor is used, the current flowing between the source and the drain flows on the surface of a semiconductor substrate and is, therefore, easily influenced by a crystal lattice defect which exists on the surface of the semiconductor substrate. As a result, in this case, flicker noise characteristics (also referred to as 1/f noise characteristics) deteriorate compared to the case where the bipolar transistor is used.
Moreover, in comparison between mismatch characteristics (the difference in threshold voltages in a pair transistor) which are important in the analog circuit, the characteristics of the MOS transistor are inferior to the characteristics of the bipolar transistor. In the case of the MOS transistor, the difference in threshold voltages of a pair transistor (hereinafter denoted by ΔVth) is influenced by many factors such as variation in the size of a gate electrode, variation in the thickness of a gate insulating film, variation in a concentration in a well surface, and variation in a dopant concentration in a gate polysilicon electrode. On the other hand, in the case of the bipolar transistor, the difference in threshold voltages of a pair transistor (hereinafter denoted by ΔVbe) depends on variation in the area of a junction between the emitter and the base and variation in a dopant concentration between the emitter and the base, so that ΔVbe is smaller than ΔVth.
Accordingly, it is understood that use of the bipolar transistor is more advantageous than use of the MOS transistor in order to increase the performance of the analog circuit (for decreasing power consumption, noise, variation, and others).
However, as described as above, the CMOS is used in the digital circuit. If the bipolar transistor is to be embedded in the digital circuit, a bipolar transistor process becomes necessary in addition to the CMOS process, which causes problems such as increased cost due to an increase in the number of steps for the process, and deterioration of the characteristics of the MOS transistor due to the addition of thermal treatment and processes for forming the bipolar transistor. Moreover, since the area of the bipolar transistor is larger than that of the MOS transistor, there is a problem of an increase in cost due to an increase in the area of a chip.
Conventionally, as a method of decreasing the area of the bipolar transistor, a technique has been proposed which significantly decreases the area of an isolation region between adjacent devices by forming a trench in the isolation region (hereinafter referred to as a trench isolation structure). As for the technique of the trench isolation structure, Patent Literature (PTL) 1 discloses a doping method with regard to a transistor having the trench isolation structure. This method can decrease the area of the isolation region, as well as improving electrical isolation between the adjacent devices. Hereafter, the doping method with regard to the transistor having the trench isolation structure disclosed in PTL 1 will be described with reference to FIG. 6. FIG. 6 shows a cross-sectional view showing processes of the doping method with regard to the transistor having the trench isolation structure disclosed in PTL 1.
First, as shown in (a) in FIG. 6, an entire surface of a p-type substrate 201 is oxidized to form a silicon dioxide layer 202, and a silicon nitride layer 203 and a silicon dioxide layer 204 are sequentially deposited on the silicon dioxide layer 202. Here, the silicon dioxide layer 204 is a film formed by decomposing tetraethyl orthosilicate (hereinafter referred to as “TEOS”).
Next, as shown in (b) in FIG. 6, by etching the silicon dioxide layer 202, the silicon nitride layer 203, and the silicon dioxide layer 204, a window 210 (the width is approximately 1 μm) defined by vertical sidewalls 211 and a horizontal bottom face 212 is formed.
Next, as shown in (c) in FIG. 6, boron ion implantation is performed to the p-type substrate 201 from the window 210 using boron as a p-type dopant. The boron ion implantation is successively performed twice; the first ion implantation is performed to reach a depth of 150 nm as indicated by the dotted line A in the diagram, and the second implantation is performed to reach a depth of 400 nm as indicated by the dotted line B in the diagram. Subsequently, desired thermal treatment is performed so that a sufficient dopant concentration can be obtained along the sidewalls of the isolation trench.
Next, as shown in (d) in FIG. 6, the opening of the window 210 is covered by a TEOS layer 205. Subsequently, anisotropic dry etching is performed to the TEOS layer 205 such that only a portion that is deposited on the sidewalls 211 of the window 210 remains in the TEOS layer 205. With this, as shown in (e) in FIG. 6, a TEOS edge portion 205a is formed and the width of the window 210 is decreased. At this time, the sidewalls 211 are positioned apart from the ends of the narrowed window 210 by a distance y. In other words, the width of the window 210 is narrowed by 2y. Here, the value y depends on the thickness of the TEOS layer 205. If the TEOS edge portion 205a is not present, the isolation trench is formed within the range between vertical lines 221 and 222 in (e) in FIG. 6. However, by forming the TEOS edge portion 205a, the isolation trench is formed narrower and the sidewalls of the isolation trench are positioned along vertical lines 223 and 224. Accordingly, the TEOS edge portion 205a is formed to narrow the window 210, so that much highly-concentrated boron can be implanted into the sidewalls of the isolation trench. That is, an amount of the deposited TEOS (the size of the edge portion 205a) controls the dopant concentration in the sidewalls.
Next, as shown in (f) in FIG. 6, by etching the p-type substrate 201 to a depth of approximately 600 nm using the anisotropic dry etching, an isolation trench 230 defined by sidewalls 231 and a bottom portion 232 is formed. Following the anisotropic dry etching, the TEOS layer 204 and the TEOS edge portion 205a are completely removed by etching using buffered hydrofluoric acid. At this time, p+-type regions 241 and 242 are formed at sidewall portions of the isolation trench 230.
Next, as shown in (g) in FIG. 6, by oxidizing the surface of the isolation trench 230, a silicon dioxide layer 250 that is as thin as 100 nm is formed on the surface of the isolation trench 230. Subsequently, boron ion implantation is performed again to increase the boron concentration at the bottom portion of the isolation trench 230 for the purpose of preventing an inversion layer from being formed in the region.
Next, as shown in (h) in FIG. 6, an insulating material 260 is uniformly deposited on the entire surface of a wafer so as to fill the isolation trench 230. This not only fills the isolation trench 230 but forms a flat surface.
Next, as shown in (i) in FIG. 6, anisotropic dry etching is performed until the silicon nitride layer 203 is exposed, and then the silicon nitride layer 203 is removed by etching using hot phosphoric acid. As a result, uniformed structure is obtained.
With the above described processes, a p+-type region (shaded areas in (h) and (i) in FIG. 6) is formed in each of the sidewalls 231 and the bottom portion 232 of the isolation trench 230. This allows the dopant concentration of boron that exists in the p-type substrate 201 to be sufficient for cancelling segregation into the silicon dioxide film 250 in the isolation trench 230, thereby preventing inversion of the p-type region to an n-type region in the periphery of the isolation trench 230. Accordingly, since a conduction path between two n-type regions on the both sides of the isolation trench 230 can be removed, an excellent isolation between the adjacent devices can be achieved.